STOP=Val_0x0, CMD=Val_0x0, RESTART=Val_0x0
Rx/Tx Data Buffer and Command Register
| DAT | This field contains the data to be transmitted or received on the I2C bus. If a write to this register is performed and a read is needed, field DAT is ignored by the I2C. If a read is preformed, these bits return the value of data received on the I2C interface. |
| CMD | This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the Tx FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a ‘don’t care’ because writes to this register are not required. In slave-transmitter mode, a 0 indicates that the data in I2C_DATA_CMD[DAT] bit is to be transmitted. When this bit is programmed attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (I2C_RAW_INTR_STAT[TX_ABRT] bit), unless the I2C_TAR[SPECIAL] bit has been cleared. If a 1 is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. 0 (Val_0x0): Master write command 1 (Val_0x1): Master read command |
| STOP | This bit controls whether a STOP condition is issued after the byte is sent or received. 0 (Val_0x0): STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO 1 (Val_0x1): STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. |
| RESTART | This bit controls whether a RESTART condition is issued before the byte is sent or received. 0 (Val_0x0): If I2C_CON[IC_RESTART_EN] bit is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 1 (Val_0x1): If I2C_CON[IC_RESTART_EN] bit is 1, a RESTART is issued before the data is sent/received (according to the value of bit CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. |